ECE3055 Fall'99 Homework Assignment #1 - ANSWERS

Due before 3:00 p.m. Tuesday 2/8/00

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#1.  Consider the following instructions for a pipelined MIPS
processor with no data-forwarding or hazard-detection circuits:

  add   $s0, $t0, $t1
  sub   $t2, $s0, $t3
  
[ 2 ]   How many NOP's would have to be added between the two
instructions to prevent an error due the data dependency (or hazard)?

#2.  Consider the following instructions for a pipelined MIPS
processor with no data-forwarding or hazard-detection circuits:

  add   $s0, $t0, $t1
  add   $s1, $t0, $t2
  sub   $t2, $s0, $t3
  
[ 1 ]   How many NOP's would have to be added between the first and
last instructions to prevent an error due the data dependency (or
hazard)?

[y|*] Could the hazard be resolved by a different assembler technique
that would not slow down the program (Y for "yes", N for "no")?

#3.  Consider the following instructions for a pipelined MIPS
processor:

  lw   $t0, 4($t1)
  sw   $t0, 4($t2)
  
[ 2 ]  How many NOP's would have to be added between the two
instructions to prevent an error due the data dependency (or hazard)
if the CPU did not have a data forwarding unit?

[ 0 ]  How many NOP's would have to be added between the two
instructions to prevent an error due the data dependency (or hazard) 
if the CPU did have a data forwarding unit? {assume no hazard detect}

#4.  Match up the following answers with the questions below.

A. Control hazard
B. Structural hazard  
C. Data dependency   { is a Structural Hazard }
D. A stall or bubble
E. Dynamic branch prediction
F. Forwarding

[ B | C ]  Immediate use of data from a load word instruction.
[ E     ]  Predicting a branch direction based on previous directions.
[ C | B ]  Immediate use of a register value that was just written.
[ F     ]  Feeding back the output from the ALU to one of the ALU inputs.
[ D     ]  Halting the IF and EX stages while letting other stages execute.
[ A ]  A branch instruction whose direction was not predicted.

#5.  What will the operating system do:

  A. Save the state of the process so it can be restarted later.
  B. Halt execution and send an error message to the user.

in a pipelined machine when the following events occur:

[ B ]  An ALU overflow.
[ A ]  An I/O interrupt.
[ B ]  An illegal instruction.
[ B ]  An illegal memory address.
[ A ]  An operating system service call.

#6.  In what stage do the following appear in the MIPS architecture?

Answers: IF, ID, EX, MEM, WB

[ EX  ]  Forwarding Unit
[ ID  ]  Hazard detection unit
[ MEM ]  Data memory
[ IF  ]  Program memory
[ ID  ]  (CPU) Control
[ WB  ]  Register writing from memory or ALU result
[ ID  ]  Register writing of immediate data
[ EX  ]  ALU
[ ID  ]  Branch direction unit (=)

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