ECE 2030a: Introduction to Computer Engineering

Dr. John A. Copeland

Spring 2004

Schedule      Reading Assignments    Supplement Reading     Slides    

Q&A       2001       2002
     Quiz Answers (2001, 2002 & 2004)


Homework-1 due Friday Jan. 16 in class (Answers).

Homework-2 due Wednesday Jan. 21 in class (Answers).

Homework-3 due Monday Jan. 26 in class (Answers).

Homework-4 due Friday Feb. 6 in class (Answers).

Homework-5 due Wednesday Feb. 11 in class (Answers).

Homework-6 bring to class Monday for discussion, turn in Friday Feb. 27 (Answers: PDF or PPT).

Homework-7 due Wednesday March 3 in class
(Answers).

Homework-8 due Friday March 26 in class
(Answers) Datapath Control line Problems and Answers.

Homework-9 due Friday April 19 in class (Answers).


Year 2001 homework problems directory.

Year 2002 homework problems directory.


The 2030 Help Lab is open in Van Leer C-448 every day Mon.-Fri. (schedule and GTA's, scroll down to bottom).

You can find additional study material and solutions to some textbook problems at Prentice-Hall Companion Web Gallery (link updated 1/21/04)

Solutions for Chap. 4 - Sequential Circuits: ftp://ftp.prenhall.com/pub/esm/electrical_and_computer_engineering.s-045/mano/logic_computer_design_fund_2e/solutions/solu_ch4.pdf


Office Hours in GCATT 579: by appointment (404 894-5177, or copeland@ece.gatech.edu) or before class in Van Leer 449c.

Class Hours:  MWF from 9:05-9:55 a.m. in Bunger Henry 360

Text and Other Resources:

Course Prerequisites:  CS 1301

Course Website:  General web site for all sections of ECE2030
       http://www.ece.gatech.edu/academic/courses/ece2030/

Course Outline:  Time permitting, the basic outline that will be followed is located at
       http://www.ece.gatech.edu/academic/courses/ece2030/outline/index.html

Instructor's Home Page:
       http://www.csc.gatech.edu/~copeland/
 

Course Evaluation:

Assignments 10%
In-class exams 3 x 20%
Final Exam 30%


Homework:  You may discuss homework with others to help understand the problems and material, but, are required to complete your own homework.  Homework is to be handed in at the beginning of the lecture on the given due date.  Late homework will not be accepted unless accompanied by a written explanation of why it is late, and even then may get half-credit.

Missed Exam Policy:  Exams are taken at the scheduled class times and the scheduled final period.  A missed exam will be recorded as a zero.  Family deaths and extreme medical emergencies when documented may be handled in a special way.

Attendance:  Since class lectures include material that is not included in the book, class attendance is required. If a class is missed, a student should make arrangements to get notes from other students. The importance of regular class attendance and good note taking cannot be understated.

Email:  All students are expected to read their email at least once a day during the week for various announcements and postings.

Academic Honesty:  All violations of the Georgia Tech Honor Code will be handled by referring the case directly to the Dean of Students for penalties.
 

Exams: see Schedule.

Course Lecture Slides:

Note:  Lecture slides are "incomplete" in terms of required course material and are provided as a convenience to save some time during your note taking.  You are still required to attend lectures and take your own notes or make additional notes on the provided slides.  You will have difficulty in the course if you try to rely solely on the lecture slides without attending class regularly to obtain important explanations. Slides also available from this class Web site. There is a schedule and reading assignments for the "Chapters" below.
 
Chapter # Title Lecture Version Print Versions
1
Introduction slides 2pp
2
Switch Networks and Switch Design slides 2pp
3
Boolean Algebra slides 2pp
4
Gate Design slides 2pp
5
Number Systems and Arithmetic slides 2pp
6
Combinational Logic Building Blocks slides 2pp
7
Sequential Systems - Latches & Registers slides 2pp
8
Finite State Machines (FSM) slides 2pp
9
Register Blocks: Counters, Shift, and Rotate Registers slides 2pp
10
Memory Systems slides 2pp
11
Datapath Elements slides 2pp
12
Single Cycle Datapath Unit (DPU) slides 2pp
13
Instruction Set Architecture (ISA) slides 2pp
14
Program Control, Jumping, and Branching slides 2pp
15
Procedure Calls and Subroutines slides 2pp

Interesting Links:

Online Digital Logic Simulator
Message to aliens - notice the binary counting for numbers used


Disclaimer:

This web page is supplied as an extra courtesy.  If any discrepancies exists between this web page and the material or discussions from class, then the material and discussions from class override what is given here.